1. Field of the Invention
The present invention relates to the field of digital electronics, and more particularly to register cells in digital computer architectures.
2. Description of the Related Art
Most computers, whether sequential or superscalar, have used registers to store data and instructions during execution. An instruction unit within a microprocessor, for example, may receive an opcode to add two values, and then the two values to be added. In response, the instruction unit may store the first value in a particular register, and then add the second number to the contents of the register.
The registers themselves have traditionally been structured much like RAMs, although with far fewer locations. For example, some computers have used either eight or sixteen registers, specified by a three-bit or a four-bit address respectively. Instruction units that use registers, such as arithmetic logic units, typically provide both the data value and/or the register address to the register file.
Each register has typically been implemented as a number of cells, one cell for each bit of the register value. One common implementation of a register file cell has been the six transistor static RAM (SRAM) cell, or "6-T," memory cell. Like RAM cells, each register file cell in a 6-T memory cell contains a pair of pass transistors, gated by a common word line associated with a particular bit of a particular register. Each 6-T memory cell also contains a pair of cross-coupled inverters between two internal nodes, ensuring that one of the nodes has a high voltage and the other node has a low voltage. Additionally, each of the inverters has been implemented as a CMOS transistor pair where each individual pass transistor couples one of the internal nodes to one of the bit lines.
Writing to the register file has typically involved driving the register address onto the word lines within the register file, and driving the bits of the data value onto the bit lines within the register file, much like writing to a RAM. The word lines that receive a high word line voltage enable the corresponding pass transistors, allowing the voltage on the bit lines to flow onto the internal nodes. Similarly, reading from the register file has also typically involved driving the register address onto the word lines within the register file. Reading the bits of the data value from the internal nodes onto the bit lines within the register file is much like reading from a RAM. The word lines that receive a high word line voltage enable the corresponding pass transistors, allowing the voltage on the internal nodes to flow onto the bit lines. In contrast to larger SRAMs, however, register files often have multiple read and write ports to support a higher read/write bandwidth.
Many of the inherent latencies of RAMs are applicable in register files as well. For example, the cross-coupled inverters within each cell are commonly fabricated very small on the die, to allow for greater device density. Consequently, during a read operation, in which bits of the data value from the internal nodes are driven onto bit lines, the small inverters are very weak drivers and have difficulty bringing the voltage on the bit lines to the proper voltage within a reasonable amount of time. Sense amplifiers are used because they detect minute amounts of difference in voltage (or current) on the bit lines, and respond by magnifying that difference.
Sense amplifiers typically have an inherent delay to prevent a response to spurious voltages (such as noise, or residual voltages from previous accesses) on the bit lines. This delay prevents the triggering of the sense amplifier until the voltage on the bit lines is known to relate to the voltage from the desired cell. In some register files, the delay has been implemented with respect to a clock; in other register files, the delay has been implemented with respect to a logical OR of the register address bits. In either case, the delay has added to the latency of the register file. Such delays in register files are even more detrimental to overall performance than delays in RAMs since register files are used on nearly every instruction while memory accesses may not be.
Similar latencies occur in the register files during write operations. A write driver applies a differential voltage onto the bit lines coupled to the cell to drive a bit of the register value as a differential voltage onto the internal nodes of a register cell. However, the bit lines can be quite long, since they are also coupled to the corresponding cell of each of the other registers. Consequently, the bit lines have a capacitance that must be overcome by the bit drivers. Driving the differential voltage past the capacitance of the bit lines adds delay in write operations.
The typical register file for the above prior systems is not optimal for a new logic style known as N-NARY logic. N-NARY logic is disclosed in copending applications, U.S. patent application Ser. No. 09/019,244, filed Feb. 5, 1998, entitled "Method and Apparatus for a N-NARY logic circuit using 1ofN encoding," and U.S. patent application Ser. No. 09/179,330 filed Oct. 27, 1998, entitled "Method and Apparatus for Logic Synchronization," both of which are incorporated by reference into this application. Briefly, the N-NARY logic style uses multiple wires to represent each signal. The value of a signal is determined by selecting one of the wires belonging to the signal. Moreover, each signal contains any number of bits of data, not merely one bit of data. Using a standard register file in an N-NARY logic design would require additional logic to transform the N-NARY signals into bits on a write operation, and then to transform the bits into N-NARY signals on a read operation. The delay cost of such additional logic reduces the performance advantages of the N-NARY logic family.
The present invention addresses the delays inherent in standard register files and also accommodates N-NARY logic signals without the need for the translation logic described above.